COMPANY

OVERVIEW

NAVIGATION

Supriya Estates, Plot #5,6,7 Navkhalsa Village, Gachibowli, Hyderabad - 500032,

Telangana, India

Telephone:  +91 9642788900                      

© 2016 | PRIVACY POLICY

SYSTEM DESIGN

System Design

PCB

Experienced team of engineers with hands-on experience on System design of varied complexity

Hands-on development experience on PCB for SoC and prototyping

Skilled to deliver SoC, non-SoC platforms on-time and aid time to market

PCB Fabrication, PCB assembly and Testing) for Engineering prototypes and production PCB: Up to 18 layers of PCB design and expertise in form factor

PCB layout Design, Design Analysis (Signal Integrity Analysis, EMI analysis, Thermal Analysis, Reliability analysis)

Architecture to netlist, Integration of IP’s, Optimizing on chip Buses, architecture and High Speed interface. Skilled to deliver SoC from concept to silicon on-time and aid time to market. Hand-on development experience on wireless, broadband and networking SoCs.

IP/ASIC Design

IP/ASIC Verification

Verification environment development using Verilog, system Verilog, c, c++

RTL Coding in Verilog and VHDL.

Behavioral model for verification.

Emulation/Target Board for ASIC/IP validation.

Formal Verification: RTL, netlist and at various stages of implementation.

RTL/Pre-Layout/Post-Layout netlist verification.

Synthesis.

IP Integration at SoC Level and Verification.

ASIC Verification Methodologies: VMM, OVM & AVM bringing about re-usability & scalability

Module, subsystem and system level verification

BFMs for all industry standard protocols, interfaces and on-chip buses

ASIC DESIGN

FPGA

RTL Coding in Verilog and VHDL.

IP Integration at SoC Level and Verification.

Behavioral model for verification.

Verification Suite development and Automation of the verification enviornment.

Emulation/Target Board for ASIC/IP validation.

Formal Verification: RTL, netlist and at various stages of implementation.

RTL/Pre-Layout/Post-Layout netlist verification.

Synthesis.

Selection of FPGA/CPLD devices for specification, optimum speed/power performance within costconstraints.

Systemetic and Qualitative approach for FPGA implementations.

Expertise in emulation environment for multi-million gate System On Chip designs.

Mapping Designs to target FPGA/CPLD and physical synthesis.

Integration of IP blocks and system level functional simulation.

Design and Implementation of IP blocks.

Exposure to Devices and EDA tools from various vendors (XILINX, ALTERA, Lattice, Actel).

Innovative target board design techniques to enable emulation system seamless interfacing with real time test equipments and debuggers.

PCB Design

FPGA Design

FPGA  Based Verification